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| e application note ap-523 pentium pro processor power distribution guidelines order number: 242764-001 november 1995
information in this document is provided in connection with intel products. intel assumes no liability whatsoever, including infringement of any patent or copyright, for sale and use of intel products except as provided in intel's terms and conditions of sale for such products. intel corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. intel retains the right to make changes to these specifications at any time, without notice. microcomputer products may have minor variations to this specification known as errata. contact your local intel sales office or your distributor to obtain the latest specifications before placing your product order. mds is an ordering code only and is not used as a product name or trademark of intel corporation. since the publication of documents referenced in this document, registration of the pentium and icomp trademarks has been issued to intel corporation. *other brands and names are the property of their respective owners. additional copies of this document or other intel literature may be obtained from: intel corporation literature sales p.o. box 7641 mt. prospect, il 60056-7641 or call 1-800-879-4683 copyright ? intel corporation 1995 e ap-523 3 contents page page 1.0. introduction ...............................................5 1.1. terminology....................................................5 1.2. references .....................................................5 2.0. typical power distribution ..................5 3.0. pentium ? pro processor power requirements..............................................6 3.1. voltage tolerance ..........................................7 3.2. multiple voltages ............................................8 3.3. voltage sequencing .......................................9 4.0. meeting the pentium ? pro processor power requirements ....14 4.1. voltage budgeting ........................................14 4.2. supplying power...........................................15 4.3. decoupling technologies and transient response .....................................................17 4.4. power planes or islands...............................22 5.0. the gtl+ bus power requirements..23 5.1. tolerance......................................................24 5.2. reference voltage........................................24 6.0. meeting the gtl+ power requirements............................................24 6.1. generating v tt ............................................24 6.2. distributing v tt ............................................24 6.3. generating and distributing v ref ...............25 7.0. recommendations ...................................26 7.1. v cc s............................................................26 7.2. v cc p............................................................26 7.3. v tt ...............................................................27 7.4. v ref ............................................................27 7.5. component models ......................................28 8.0. measuring transients...........................29 9.0. existing technology for a pentium a a pro processor system design ...........................................................29 9.1. solutions for v cc p ......................................29 9.2. linear regulators for v tt ............................29 9.3. termination resistors...................................29 10.0. dc-to-dc converter specifications29 10.1. electrical specifications..............................29 10.2. mechanical requirements ..........................32 10.3. tests and standards ..................................36 11.0 pentium ? pro processor power distribution network modeling.....................38 11.1. using the power distribution model ...........38 11.2. power distribution model............................39 figures figure 1. ideal cpu power supply scheme ........5 figure 2. physical power distribution...................6 figure 3. a detailed power distribution model.....6 figure 4. transient types.....................................7 figure 5. multiple voltage die...............................8 figure 6. power pins of the pentium pro processor package - top view (through the package) .........................9 figure 7. voltage sequencing example .............10 figure 8. tolerant esd diodes...........................11 figure 9. gtl+ esd diodes...............................11 figure 10. timing diagram of compatibility pins12 figure 11. schematic of pin sharing ..................13 figure 12. system design model .......................15 figure 13. remote sense...................................15 figure 14. location of capacitance in a power model with a dc-to-dc converter ......17 figure 15. effect of transients on a power supply .................................................18 figure 16. esr cylindrical capacitor.................19 figure 17. a capacitor model.............................19 figure 18. esr required for various current demands..............................................19 figure 19. capacitance required vs. esr at 8.5a, 60 mv d v and 30 m s d t...............20 figure 20. a pentium ? pro processor voltage island...................................................22 ap-523 e 4 figure 21. 1206 capacitor pad and via layouts23 figure 22. v ref ................................................. 25 figure 23. local regulation ............................... 26 figure 24. generating v ref ............................. 28 figure 25. pin orientation (top view) ............... 33 figure 26. module printed wiring board (dimensions in mm) ........................... 34 figure 27. module connector features (dimensions in mm) ........................... 34 figure 28. mating header (dimensions in mm) . 35 figure 29. alternative mounting configuration - baseboard pattern (top view, dimensions in inches)........................ 37 figure 30. socketed pentium a pro processor power distribution model schematic . 39 figure 31. power distribution model short-circuit current................................................ 39 tables table 1. timing parameters of compatibility pins13 table 2. a sample voltage budget..................... 14 table 3. efficiency of a linear regulator............ 17 table 4. estimating v tt current ........................ 24 table 5. various component models used at intel (not vendor specifications)......... 28 table 6. 150 mhz, 256-kbyte l2 cache pentium pro processor voltage and current specifications ...................................... 30 table 7. dc output current............................... 30 table 8. voltage ranges ................................... 31 table 9. voltage identification code ................... 31 table 10. pin definitions .................................... 33 table 11. environmental guidelines .................. 36 e ap-523 5 1.0. introduction as computer performance demands increase, new, higher speed logic with increased density is developed to fulfill these needs. to reduce their overall power dissipation, modern microprocessors are being designed with lower voltage implementations. this in turn requires power supplies to provide lower voltages with higher current capability. because of this, processor power is now becoming a significant portion of the system design, and demands special attention. power distribution requires careful design practices now more than ever. the pentium ? pro processor has unique requirements for the voltages supplied to it, as well as a new bus implementation, called gtl+, which requires a voltage supply of its own. for most personal computer designs, a power plane with a mix of high frequency and bulk decoupling capacitors spread evenly across the system board is a low cost way to ensure sufficient power distribution. as the current differences between the low power state and the high power state increase, the cost of the power distribution system becomes significant enough to merit careful calculation. centralized distribution of power, for example, may no longer be the most cost effective solution to power distribution. another side effect of lowering voltages of some components is the existence of multiple voltages within the system. on a basic pentium pro processor-based system board there will be 1.5v for gtl+ termination, 2.5v-3.5v for the processor, 3.3v for the chipset and the l2 cache, and 5v for other components. the possibility that any of these voltages may come up before another must be taken into account. this is discussed in section 3.3. the reader should be familiar with basic electrical engineering theory, as the first sections of this document will explain in detail the issues involved in designing a system with proper power distribution. the last sections will offer specific solutions for a system containing any number of pentium pro processors. this includes a specification for a dc-to-dc converter module. 1.1. terminology power-good or pwrgood is an active high signal in the system which indicates that all of the supplies and clocks within the system have become stable. pwrgood should go active some constant time after 5v, 3.3v and v cc p are stable and should go inactive any time any of these voltages fail their specifications. the time constant should be set such that, in a working system, all clocks and other supply levels have reached a stable condition before pwrgood goes active. v cc p is the processor cores v cc . v cc s is always 3.3v. gtl+ is the technology used for the bus between the pentium pro processor and its chipset. the gtl+ bus and the processor bus are therefore synonymous. 1.2. references the pentium ? pro processor developers manual, volume 1: specifications (order number 242690) is referenced throughout this document. 2.0. typical power distribution + - cpu figure 1. ideal cpu power supply scheme power distribution is generally thought of as getting power to the parts that need it . most digital designers typically begin by assuming that an ideal supply will be provided, and plan their schematics with little thought to power distribution until the end. the printed circuit board designers attempt to create the ideal supply with two power planes in the pcb or by using large width traces to distribute power. high frequency noise created when logic gates switch is controlled with high frequency ceramic capacitors, which are in turn recharged from bulk capacitors (such as tantalum capacitors). various rule of thumb methods exist for determining the amount of each type of capacitance that is required. for pentium pro processor designs the system designer will need to reach beyond the rule of thumb and architect the power distribution system with the specifications of the pentium pro processor in mind. ap-523 e 6 figure 2. physical power distribution figure 1 shows the ideal power model. however, in real systems, the power distribution scheme typically appears as in figure 2. this system has physical components such as cables, connectors, the pcb, and the component packages. to completely model this system, one must include the inductance and resistance which exists in the cables, connectors, pcb, and the pins and body of components such as sockets and capacitors. a more detailed model showing these effects is shown in figure 3. in the past, voltage drops due to inductance (v = ldi/dt) and resistance (v = ir) have been nearly negligible relative to the tolerance of components in most systems. this has caused the creation of simple rules for decoupling. for example, with the current at 1 amp, and the tolerance at 250 mv (5% of 5v), one could easily ignore the effects of 25 m w of resistance in the distribution path. however, at 10 amps, this ir drop is equal to the 250 mv tolerance. similarly, 250 ph of inductance can typically be ignored in a power distribution system, unless current transients of 1 amp/ns exist, as they do when using the pentium pro processor. the ldi/dt drop in this case is also equal to 250 mv. cpu package + - power supply c die c pkg c hf c bulk l bond l pin+socket l board l cable r cable r board die figure 3. a detailed power distribution model the high value of the pentium pro processor current and the high rate of change of the current must both be taken into account for a successful design. the requirements of the pentium pro processor are described in section 3, and meeting these requirements is discussed step by step in section 4. 3.0. pentium ? pro processor power requirements this section describes the issues related to supplying power to a pentium pro processor using approximate e ap-523 7 values. however, actual specifications are documented in the pentium pro a processor developers manual, volume 1. the pentium pro processor with 256-kbyte cache operates at 3.1v, compared with 3.3v for a pentium 815/100 processor, and 5v for previous intel processors. the tolerance requirement remains at 5%, while the average current demand is approximately 3 times that of the pentium 815/100 processor. in addition, the pentium pro processor shuts off unused units to conserve power, and includes features such as stop clock and auto halt, which create load-change transients as high as 8.5 amps in just one or two bus clock cycles. in this document, a load-change transient is a change from one current requirement (averaged over many clocks) to another. figure 4 illustrates the v cc and v ss currents of a processor coming out of a low power state and then running in a full power state. the averaged v cc is shown to illustrate what is meant by the term load-change transient . v ss current is higher than v cc current in figure 4 due to power being delivered from the gtl+ bus power supply through the pentium pro processor gtl+ buffers. other transients which must be understood are the switching transients which occur at the processor clock rate, also shown in figure 4. time (ns) v ss current v cc current averaged v cc current load-change transient switching transient switching transient figure 4. transient types future pentium pro family processors may have a requirement for a separate 3.3v supply for the l2 cache die, as well as higher current requirements, and different voltages for the cpu die. the gtl+ bus is terminated at each end to a voltage source called v tt . v tt is nominally 1.5v, with a tolerance of 150 mv. this bus implementation allows up to 8 loads, and may be run at speeds up to 66 mhz. just as the processor can start and stop executing within a few clock cycles, the bus usage will follow. each of these concepts is discussed in the following sections. the gtl+ power requirements are discussed in section 5 and section 6. 3.1. voltage tolerance the processor voltage tolerance specification has remained at 5%, while the voltage specification has decreased. this causes the absolute tolerance requirement to decrease. for example, 5% of 5v is 250 mv while 5% of 3.1v is 155 mv. it is important to note ap-523 e 8 that this tolerance specification covers all voltage anomalies, including power supply ripple, power supply tolerance, current transient response, and noise. failure to meet this specification on the low end will result in transistors slowing down and not meeting timing specifications. not meeting the specification on the high end can induce electro-migration, causing damage or reducing the life of the processor. 3.2. multiple voltages l2 cache cpu figure 5. multiple voltage die while the pentium pro processor with a 256-kbyte l2 cache runs at 3.1v ( ), it consists of two separate die. the processor core and the 256-kbyte l2 cache die are each designed for 3.1v, but future cache die may be designed to run at 3.3v. also, future pentium pro processor components will run at a different voltage than 3.1v. figure 5 shows a pentium pro processor package with the two types of voltage combinations shown beneath it. the pentium pro processor definition specifies that every l2 will run on either the same supply voltage as the processor core (which may change in the future) or at 3.3v. see the flexible motherboard guidelines in the pentium a pro processor developers manual, volume 1 for details. the pentium pro processor package is designed to support future cache die by adding separate 3.3v cache support pins to the package. these pins are called v cc s pins, while the primary voltage is supplied on the v cc p pins. see figure 6 for the location of these pins. for a system to operate seamlessly with a pentium pro processor with a 512-kbyte l2 cache, the v cc s pins simply need to be connected to a well decoupled 3.3v supply. the cache die of each component is bonded internally to receive power either from the cache support pins, or from the main power source as required by the device. future cache die on v cc s are not expected to exceed a maximum average current (over many cycles) of 2.4a. note that in components in which the l2 is receiving current from the v cc s pins, the v cc p current will be decreased. the maximum power of a pentium pro processor is specified as the sum of the maximum power of each die, not by the maximum current specification of each voltage source. e ap-523 9 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa aaaa 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other than 3.1v. this may range from 2.5v to 3.5v. to support this level of upgrade potential, the power source for the main processor supply should be designed with the ability to be easily configured to provide a voltage within the range of 2.4v to 3.5v. note that the cache will either run at the same voltage as the processor, or at 3.3v, using the cache support pins. one easy way to support this range is with a replaceable power module. another is by changing the set point of the regulator via a variable resistor, or by using the processors voltage id pins with a resistor tree or a digital to analog converter (dac). the voltage id scheme is described fully in the pentium a pro processor developers manual, volume 1 . intel has worked with power supply vendors to create replaceable voltage regulators which support voltage selection. see your local field applications engineer for assistance. another voltage is required for the gtl+ bus. this level is called v tt , and is set at 1.5v. this voltage is discussed in section 5, but is important in the discussion of voltage sequencing in section 3.3 as well. 3.3. voltage sequencing when designing a system with multiple voltages, there is always the issue of ensuring that no damage occurs to the system during voltage sequencing. voltage sequencing is the timing relationship between two or more voltages, such as 3.3v and v cc p. sequencing applies when the power supply is turned on or off, or enters a failure ap-523 e 10 condi tion. sequencing applies to the power voltage levels and the levels of certain other crucial signals. figure 7 shows an example of power voltage sequencing. here voltage levels a and b are shown to trade places with each other. on power-on, a-b may be larger at any point than they will be once they reach their nominal levels. on power-off, the voltage b input may actually be higher than the voltage a input for some period of time. the pentium pro processor, gtl+ bus, and intels chipsets have been designed such that no additional circuitry is required in the power system to ensure the order of voltage sequenc ing. however, systems should be designed such that neither supply stays on permanently while the other is off. the long term reliability of the component can be compromised by excessive exposure to these conditions. the discussion following is simplified by assuming the worst case which is one voltage on while the other is off. see figure 8 and figure 9 for highly simplified models of the buffers that show the esd protection diodes. this model is provided for discussion purposes only and is not meant to imply any implementation scheme. a nom b nom a rising first, falling first b rises later, falls later time v o l t s b > a a-b > a nom -b nom figure 7. voltage sequencing example e ap-523 11 vcc p l pin esd diodes p a c k a g e b o u n d a r y figure 8. tolerant esd diodes 3.3.1. 3.3v tolerant signals the 3.3v tolerant buffers are open drain. when the v cc p supply is on, and the 3.3v supply is off, the esd protection diodes of the buffers are reverse biased and no power is supplied to the signal lines. as the processor sees reset#, the outputs switch to the high or inactive state so bus contention after 3.3v comes up is avoided. if the 3.3v supply is on while the v cc p supply is off, the 3.3v supply will deliver current to the pentium pro processor core through the string of three esd protection diodes connecting the pads to v cc . if a pull-up is used for the high level of the signals, then 150 ohms will allow a maximum of only 9 ma of current to be supplied to the core per pad cell. if the inputs are driven by a cmos output, then the current from the output should be limited to 200 ma maximum output current per pentium pro processor pin. if v cc p is used as the high level for the 3.3v tolerant signals, then no sequencing issue exists. 3.3.2. gtl+ signals the gtl+ outputs are also open drain. when the v cc p supply is on and v tt is off, all inputs appear low and there will be no current flowing on the gtl+ bus. if v tt is on and v cc p is off, the gtl+ bus will attempt to power up the core through the esd protection diode. the resulting v cc level will be low enough that no significant current will be consumed by the core. 25 w w vtt vcc p driver esd diode p a c k a g e b o u n d a r y figure 9. gtl+ esd diodes note every device on the bus must have power in order for the gtl+ bus to operate properly. 3.3.3. memory side signals the 5v tolerant signals are internally buffered in a similar manner. when using 3.3v dram there are no memory side sequencing issues. when the 5v supply is on to 5v dram and the 3.3v memory controller supply is off, the cas lines may be floating. this could cause the dram to drive 5v signals to a component that has no voltage applied. the system should provide weak pull-ups to 5v on the cas lines to prevent the 5v dram devices from driving 3.3v inputs when there is no power to the memory controller. by providing the memory controller with the pwrgood signal (as described in section 1.1), it will drive the cas lines of the dram inactive, and reset the data buffers as soon as it receives 3.3v. this will hold the dram outputs off and keep the chipset buffer components in reset during a period of power supply stabilization. this includes a poor v tt that would prevent the gtl+ bus reset# signal from being created correctly. this action protects these devices from producing bus contention between themselves. 3.3.4. pci side signals pci_rst# tells all pci devices to remain in a tri-state condition. this signal will be held active by the pci bus controller when it is receiving power and its pwr_gd signal is inactive. the pci bus controller will also tri- state its signals during this time. in addition, the pci ap-523 e 12 inputs use a 5v input for their esd protection. this eliminates any issue with turning on its esd diodes. if there are 5v pci cards in the system, it would also be prudent to supply a weak pull-down on the pci_rst# line for the event that 5v is on while 3.3v is off. 3.3.5. clock input the clock input frequency must never exceed the intended final value while the pwrgood signal to the processor is active. (see terminology in section 1.1) pwrgood should be inactive anytime that v cc p or 3.3v are invalid. this can be accomplished by logically or-ing the pwrgood signals from both supplies, and connecting this output to the chipset and the pentium pro processor power-good inputs (pin names may vary) for reset generation. (in this case, pwrgood is a signal from each supply that signals when its voltage level is stable and within tolerance.) 3.3.6. clock ratio inputs the pins a20m#, ignne#, lint1, and lint0 are shared with the function for programming the pll core clock multiplier ratio. these pins control the setting of the clock multiplier ratio during reset# and until two clocks beyond the end of the reset# pulse. at all other times their functionality is defined as the compatibility signals that the pins are named after. these signals have been made 3.3v tolerant so that they may be driven by existing logic devices. this is important for both functions of the pins. figure 10 shows the timing relationship required for the clock ratio signals with respect to reset# and bclk. table 1 shows the timing parameters. note that the minimum setup time for these signals is 1 ms. this table also shows the timing relationship of the compatibility signals. a signal called creset# (cmos reset) is shown, with the timing needed for controlling the multiplexing function required to share the pins. this may be provided by the chipset. creset# final ratio compatibility bclk reset# ratio pins# t1 t2 t3 t4 final ratio t5 figure 10. timing diagram of compatibility pins e ap-523 13 table 1. timing parameters of compatibility pins t# parameter minimum maximum units t1 reset# active to creset# 10 ns t2 reset# active to ratio delay 5 bclks t3 bclk to creset# inactive 10 ns t4 bclk to compatibility 20 bclks t5 ratio setup to reset# rising 1 ms using creset#, the circuit in figure 11 can be used to share the pins. the pins of the processors are bussed together to allow any one of them to be the compatibility processor. the component used as the multiplexer must not be powered by more than 3.3v in order to meet the 3.3v tolerant buffer specifications of the pentium pro processor. the multiplexer output current should be limited to 200 ma maximum, in case the 3.1v supply does not come up. the pull-down resistors between the multiplexer and the processor (1k ohms) forces a ratio of 2:1 into the processor in the event that the pentium pro processor powers up before the multiplexer and/or the chipset. this prevents the processor from ever seeing a ratio higher than the final ratio. these are unnecessary if another known ground path through the multiplexer exists when 3.3v is off. if the multiplexer were powered by v cc p, creset# would still be unknown until the 3.3v supply came up to power the chipset. a pull-down can be used on creset# instead of the four between the multiplexer and the pentium pro processor in this case. in this case, the multiplexer must be designed such that the compatibility inputs are truly ignored as their state is unknown. in any case, the compatibility inputs to the multiplexer must meet the input specifications of the multiplexer. this may require a level translation before the multiplexer inputs unless the inputs and the signals driving them are already compatible. compatibility signals from system ratio p6 creset# p6 p6 pentium pro processor 3.3v mux figure 11. schematic of pin sharing ap-523 e 14 3.3.6.1. mixed frequency processors in order to support different frequency multipliers to each processor, the design will require four multiplexers. before implementing this strategy, one should understand how useful this will be to the operating systems running on the system. 3.3.6.2. frc mode for frc mode processors, one multiplexer will be needed per frc pair, but the multiplexer will need to be able to be clocked using bclk and meet setup and hold times to the processors. this may require the use of high speed programmable logic. 4.0. meeting the pentium ? pro processor power requirements to solve the needs of the pentium pro processor, one must merely be aware of the issues described above and design the system appropriately. this involves making many tradeoffs between power supply, distribution and decoupling technologies. this section discusses how to design a system using the more accurate power distribution model shown in figure 3, one step at a time. 4.1. voltage budgeting before beginning the design of a power distribution system one must have an idea of how the tolerance specification will be budgeted to each of the components involved. this will provide a target for each component and helps reduce iterations to reach a solution. the pentium pro processor requires that the system meet a 5% tolerance specification. this is equivalent to 155 mv above and below the nominal 3.1v. do not include voltage drops of the pentium pro processor socket, pins etc. since these are taken into account beyond the 5% tolerance specification. this is the budget the system designer has to work with which leaves the model in figure 12 to work with at the pentium pro processor socket pins. the components that should be included in a voltage budget are shown in table 2 along with example values for each. there are two budgets shown since different components are more prevalant at different times. inductive effects are significant early in a current transition while di/dt is high and are shown in the high frequency (hf) budget. capacitive effects are more important once the hf capacitors have released their charge and are shown in the low frequency (lf) budget. board resistance losses must always be included, while esr losses only need to be included for capacitors while they are delivering current. capacitor esr is shown as a loss in both budgets. this may make a good starting point for any system budget, but will be adjusted to suit that systems needs. each component is discussed in the following sections. table 2 assumes that voltage drops break down over time in a discrete manner. ultimately the power distribution should be simulated by the designer which will allow the budget to be loosened. table 2. a sample voltage budget component hf budget in mv lf budget in mv tolerance specification 155 155 regulator set point tolerance -25 -25 inductive losses in hf capacitors -60 0 hf capacitance esr -30 0 bulk capacitance esr/ capactance sag 0 -60 inductive losses in board -10 0 resistive losses in board -10 -10 ripple, noise -10 -10 margin 10 50 e ap-523 15 4.2. supplying power the start of a power distribution system is the source of power, or the power supply. the voltage required by the pentium pro processor is probably not already available from a standard supply and will need to be created as pentium pro processor designs are developed. the new voltage can be generated from an ac input (such as the line voltage) or from another dc supply. also, the voltage can be created within a central power supply unit and distributed, or created locally to the load. the many tradeoffs involved are discussed here. in order to maintain power supply tolerance, either local regulation or a power supply with remote sense capabilities is required. this is due to the higher current requirements of the pentium pro processor. typically there is a dc loss over the power distribution system due to the resistance of such things as cables, power planes, and connectors. these are the first two components of the complex model being discussed. they are shown in figure 12 as r board and r cable . + - c hf c bulk l board l cable r cable r board c p u power supply figure 12. system design model this loss can be represented as d v = i r, where d v is the voltage loss, i is the current and r is the effective resistance of the distribution system. when the average current is continuous, the power supply can be designed to compensate for this loss by setting the voltage slightly higher than the nominal value. this ensures that the voltage at the farthest reaches of the system is still within specification. however, when the current has the ability to change significantly between a high and a low state (i.e. d i is high), d v changes significantly as well. this change in voltage can be represented as d v = d i r. this loss can become significant due to the tighter tolerance specification of the pentium pro processor requiring that the total d v at the cpu socket be within 5% of the nominal voltage. local regulation is the use of a supply or regulator near the load to create the voltage needed. one practical example of this is a local dc-to-dc converter. in this application, a higher dc voltage is typically distributed to the area where the load exists and then is converted to a lower level using either a linear or a switching regulator. by distributing a lower current at a higher voltage, the unwanted losses (i x r) are minimized. (this is done in high tension lines to distribute electricity from the generating source to local residential use). more importantly however, the voltage is regulated locally which minimizes dc line losses by eliminating r cable and reducing r board on the processor voltage. if local regulation is not appropriate, then a power supply with remote sense may be used. a power supply typically regulates the voltage at its terminals before cabling to the board. again, changing distribution losses based on the current demand make it difficult to hold a tight tolerance at the load. a remote sense, shown in figure 13, solves this problem by running a separate power source load amps (large d d v) m m amps (small d d v) figure 13. remote sense connection from near the load to the feedback loop of the power supply. this line will have very low current draw ap-523 e 16 ( m amps) and will not suffer from the line losses described above. this allows the supply to regulate its output based on the voltage level at the load that is affected by the line losses. the down-side of this method is the added inductance due to cabling to a power supply and the noise induced in the remote sense feedback signal. section 4.3 explains why this is an issue. another difficulty is finding a representative load point that applies for all processors when there is more than one in the system. in either case the accuracy of this voltage can be maintained fairly easily at 2%, plus a small ripple and noise budget, under a stable load. however, further demands of the pentium pro processor will tax this supply. with the large current transients developed by the processor, extreme care must be exercised to eliminate noise coupling and ringing when using remote sense feedback. 4.2.1. local dc-to-dc converters vs. centralized power supply most desktop computers today utilize a self-contained multiple output power supply. this is convenient and cost effective as it isolates the issues of power generation from the system designer and allows the creation of a large reusable sub-system. however, lower operating voltages and increased transient response make long bus distribution schemes and self-contained supplies less suitable due to the resistance and inductance of the distribution scheme. the use of distributed local dc-to- dc converters provides another alternative. another benefit of distributed local dc-to-dc converters is upgrade potential. they allow for socketed and/or voltage selection and regulation. sockets allow modules to be added or replaced as required while self adjusting regulators can be set to meet the varying needs of the processor socket. while the decision lies in the hands of the system designer, intel recommends the use of local regulators. converter sockets meeting the upgrade specification in the pentium a pro processor developers manual, volume 1 can then be installed by each empty pentium pro processor socket to provide an inexpensive upgrade strategy. utilized pentium pro processor locations can be powered by a socketed regulator or one whose output levels can be selected. 4.2.2. ac vs. dc input voltage the new pentium pro processor dc voltage can be created directly from the line voltage or from a low voltage ac or dc tap of the central power supply. creating a dc voltage from an ac voltage is generally easier than converting from one dc level to another. this is due to the fact that a dc voltage fi rst needs to be chopped in order create an alternating voltage that can be then stepped up or down. typically however, pc power supplies today do not provide ac voltage taps to the system. creating the additional dc voltage from the line voltage requires the addition of an extra winding to the line transformer. this tends to be rather costly, and will suffer more from issues of distribution explained in the next sections. changing the output voltage in this system requires changing the transformer, which makes the design less versatile. creating the additional dc voltage from an existing dc voltage requires a dc-to-dc converter. these converters work well in the pc market as they can be designed to work off the existing 5v or 12v taps of standard pc power supplies, and can be manufactured in high volumes. they can be placed very near the pentium pro processor, thus reducing distribution loss issues, or designed into the existing power supply case. they can also be designed to have a selection of output voltages, as well. 4.2.3. linear regulators vs. switching regulators a linear regulator is a simple device that drops a variable voltage across itself in order to maintain an output voltage within tolerance regardless of load changes (within its specifications). due to the simplicity of this device, its reaction time is fairly quick, on the order of 1 m s. however, the efficiency of a linear regulator is fairly poor. its efficiency drops off as the input voltage and output voltage become farther separated as evidenced in equation 1. equation 1 loss within a linear regulator p loss ? (v in -v out ) i. the linear regulator also requires a minimum drop from the input to the output of about a diode drop (0.5v-1.0v), making it impossible to have small changes from v in to v out . e ap-523 17 table 3. efficiency of a linear regulator v out efficiency with v in of 5v power loss at 9.9 amps 3.3 66% 16.8w 3.1 62% 18.8w 2.5 50% 24.8w the efficiency of a linear regulator can be approximated by the formula efficiency = v out /v in . the power loss and efficiency are shown in the table 3 where v in has been left at 5v and the current delivered has been fixed at 9.9 amps. the power loss is fairly significant for a linear regulator. although linear regulators tend to have faster reaction times than switching regulators, the power loss in a linear regulator is high enough that the use of a switching regulator should be considered at these higher output current ratings. an 80% efficiency can be achieved using a 3.1v switching regulator at 9.9 amps. a switching regulator first chops the input voltage to make it ac-like . the faster it switches or chops, the faster the reaction time of the converter can be. the faster the reaction time, the less capacitance will be required to support it. low end switching regulators operate at a 100 khz switching rate, while high end devices start at 1 mhz. 4.3. decoupling technologies and transient response as shown earlier, inductance is also an issue in distribution of power. the inductance of the system due to cables and power planes further slows the power supply's ability to respond quickly to a current transient. package + - dc-to-dc converter c pkg c hf c bulk l bond l pin l board c die die figure 14. location of capacitance in a power model with a dc-to-dc converter decoupling a power plane can be broken into several independent parts. figure 14 shows each of the locations where capacitance could theoretically be applied. the closer to the load the capacitor is placed, the more inductance that is bypassed. by bypassing the inductance of leads, power planes etc., less capacitance is required. however, closer to the load there is less room for capacitance. therefore tradeoffs must be made. typically a digital component will cause switching transients. these are the sharp surges of current that occur at each clock edge and taper off by the end of the cycle as shown in figure 4. the pentium pro processor has been designed such that it manages the highest frequency components of the current transients. this has been accomplished by adding capacitance to the package (c pkg ) as well as directly on the die (c die ). to lower bond wire and pin inductance (l bond and l pin ) as well as the board inductance (l board ), the pentium pro processor is designed with approximately 70 ground pins and 45 power pins. (the larger number of ground pins than power pins is to account for the current ap-523 e 18 requirements of the gtl+ open drain gates). these processor design considerations reduce the current slew rate to the order of 1a/ns at the pins. outside the package, the 1a/ns current slew rate is supplied current by local high frequency, low inductance decoupling (c hf ) such as ceramic capacitors. larger bulk storage (c bulk ), such as electrolytic capacitors, supply current during longer lasting changes in current demand by the component, such as coming out of an idle condition. similarly, they act as a storage well for current when entering an idle condition from a running condition. 2.80 2.85 2.90 2.95 3.00 3.05 3.10 0 30 60 90 120 150 time (ns) v o l t a g e ( v o l t s ) c u r r e n t poorly controlled supply well controlled supply current tr ansients figure 15. effect of transients on a power supply all of this power bypassing is required due to the relatively slow speed at which a power supply or dc-to- dc converter can react. a typical voltage converter has a reaction time on the order of 1-100 m s while the processors current transients are on the order of 1 to 20 ns. bulk capacitance supplies energy from the time the high frequency decoupling capacitors are drained until the power supply can react to the demand. more correctly, the bulk capacitors in the system slow the transient requirement seen by the power source to a rate that it is able to supply, while the high frequency capacitors slow the transient requirement seen by the bulk capacitors to a rate that they can supply. figure 15 shows a poorly controlled supply versus a well- controlled supply during an increase in current demand. notice how the poorly controlled supply dips below the allowed tolerance specification. a similar situation exists as the current demand decreases. a load-change transient occurs when coming out of or entering a low power mode. for the pentium pro processor this load-change transient can be on the order of 9 amps. these are not only quick changes in current demand, but also long lasting average current requirements. this occurs when the stpclk# pin is asserted or de-asserted and during auto halt. auto halt is a low power state that the processor enters when the halt op-code is executed. note that even during normal operation the current demand can still change by as much as 7 amps as activity levels change within the pentium pro processor component. to maintain voltage tolerance during these changes in current, both high frequency decoupling capacitors and slower, high-density bulk capacitors with low esr will be required. these components need to be chosen based on a thorough analysis. e ap-523 19 4.3.1. bulk capacitance to understand why just adding more capacitance is not always effective, one must consider the effective series resistance (or esr) of the capacitance being added. this is the inherent resistance of the capacitor plate material. one way to understand where esr comes from, and how to recognize a low esr capacitor, is to analyze a cylindrical capacitor. by unrolling the metal of the capaci tor it appears as a sheet. this sheet has some linear resistance in w /inch. a longer sheet (bigger diameter capacitor) increases esr. a wider sheet (taller capacitor) decreases the esr. figure 16. esr cylindrical capacitor another effect is the fairly high inductance of the bulk capacitors. these elements can be modeled as shown in figure 17. again, this was taken from the complex model of figure 3. overcoming esr is discussed here while assuming for now that the inductance effect will be addressed by the high frequency decoupling capacitors discussed in section 4.3.2. c esr esl figure 17. a capacitor model figure 18 shows the relationship between current delivered (with a 60 mv budget) and the esr of the capacitors. as can be easily seen, even with infinite capacitance, 6 m w of esr at 10a drops the full budget of 60 mv as shown in equation 2. equation 2. esr allowed for 60 mv budget r mv i = 60 / 0.000 0.005 0.010 0.015 0.020 0.025 0.030 2.000 4.000 6.000 8.000 10.000 amps e s r r e q u i r e d i n o h m s figure 18. esr required for various current demands length width ap-523 e 20 another useful formula for estimating the amount of bulk capacitance required is shown in equation 3. this ignores the esr of the component but furnishes the amount of capacitance that would be required from an ideal component. equation 3. capacitance for an ideal capacitor c i vt = d dd d i represents the current that the bulk capacitance must be able to deliver or sink. this is equal to the difference between high and low current states since the power supply will initially continue to supply the same current that it had been prior to the load change. d v is the allowable voltage change budgeted for bulk capacitive sag (discharge) over the period d t. d t is the reaction time of the power source. assuming some representative numbers for i , d v , and d t , the capacitance required is shown by equation 4. equation 4. capacitance needed if esr is 0 ohms c a vx s f == - 85 0 060 30 10 4250 6 . . m combining the above formulas to remove the resistive drop from the budget for the bulk capacitance gives equation 5. equation 5. capacitance vs. esr c i t v i esr = - d d this equation leads to the capacitance vs. esr graph shown in figure 19, when d v is assumed to be 60 mv, i is assumed to be 8.5a, and the reaction time ( d t ) of the power source is 30 m s. the shaded area of the graph covers capacitance types that are insufficient for this application. again this provides a figure that can be used to get a feel for the type of capacitors required. for example, to satisfy this equation one could use twelve 1000 m f capacitors if the esr of each was 53 m w . the parallel resistance of 12 capacitors would be 4.4 m w and the parallel capacitance would be 12,000 m f, which falls in the white zone of the graph in figure 19. 0 5000 10000 15000 20000 25000 30000 0 . 0 0 0 0 . 0 0 1 0 . 0 0 2 0 . 0 0 3 0 . 0 0 4 0 . 0 0 5 0 . 0 0 6 resistance ( w) c a p a c i t a n c e ( m f ) figure 19. capacitance required vs. esr at 8.5a, 60 mv d d v and 30 m m s d d t e ap-523 21 this is a fairly conservative analysis. using a reaction time for a power source assumes that the power source does not compensate at all for the change in current demand until d t has passed, and then immediately is capable of delivering to that demand. also, it is unnecessarily conservative to assume that the ir drop is the full drop the whole period in which the capacitor discharges as the current drops as the capacitor discharges. to analyze the power distribution system in more detail requires running a simulation from the power source model to the pentium pro processor power model, including all board, cable, and capacitor effects. see section 7.5 for more information on component models and section 11 for the pentium pro processor power model. 4.3.2. high frequency decoupling since the bulk storage not only contains an effective series resistance, but also a fairly high inductance, these capacitors need to be assisted by other capacitors that have a lower inductance (but typically less capacitance). these high frequency capacitors will control the switching transients and hold-over the power planes during an average load change until the higher inductance capacitors can react. the 1206 surface mount package is a fairly low inductance package, and is actually lower than the inductance of an 0603 package due to the geometry of the board interconnects. for even lower inductance one can use a 0612 package since the board interconnect area gets even larger. an 0612 is the same size as the 1206 but has its pads along the long edge. the cost of these is significantly higher however due to the complexity of mass producing them. the 1206 package capacitors on the other hand are readily available and low cost. one difficulty in simulating with high frequency capacitors however, is that vendors do not readily offer a specification for the inductance of their parts. in section 7.5 are some measured values from capacitors that intel has investigated which should be verified against the vendors parts that will actually be used in any design. after calculating the number of capacitors required, one can look at the impact that averaging tolerances over many measured components has to the design and pad the design appropriately with additional components. since the capacitor inductance is package related, choose the largest value available in the package that has been chosen. the highest capacitance obtainable will be the most beneficial for the design since the amount of capacitance behind this inductance is still critical. this simple law of inductance is useful for estimating the number of high frequency capacitors required: equation 6. simple law of inductance v l di dt = v is the voltage drop that will be seen due to the inductance. a di/dt value of 0.3a/ns can be used to estimate the pentium pro processor and l is the inductance of a series combination of via, trace, and all of the high frequency capacitors in parallel. see section 4.4 for ideas on reducing via and trace inductance. once the allowable inductance for the budgeted voltage drop (due to high frequency transitions) is calculated, the number of capacitors ( n ) required can be estimated by: equation 7. number of capacitors required nll n = / where l n is the inductance of a single capacitor and l is the inductance required that was calculated above. for example, to meet a 0.3a/ns di/dt and not produce more than 60 mv of noise due to high frequency capacitor inductance (1.9 nh from table 5) one would simply plug into equation 6 and equation 7. equation 8. inductance allowed lvansnh =? = 0 060 0 3 0 2 .. . equation 9. number of capacitors for 0.2 nh n nh nh capacitors =? = 19 02 10 .. 1 footnote 1 more capacitors will actually be required to achieve the necessary capacitance prior to the voltage regulator module due to the limited space within a 1206 package. the number of capacitors required for a pentium pro processor is therefore capacitance dependent. ap-523 e 22 resistance of the high frequency capacitors can also be included in the above analysis, but the resistance and current for each capacitor are low enough that this should not be necessary. while the above calculation provides a theoretical number of capacitors required to meet the processor di/dt requirements, high frequency noise may yet persist. more capacitors may be necessary to control noise from other sources. however, mixing additional values in the design to create higher resonance points should not be useful since the capacitors described (1206 package) have very high resonant frequencies already. this is shown by using the values from table 5 in equation 10. equation 10. resonant frequency f lc mhz =? ? -- 1 2 1 20 10 110 73 96 p p ( .47 ) ( ) . note that all 1206 capacitors will have basically the same inductance value and that smaller components actually have more inductance. also, the inductance of the vias are the larger contributors and actually cause the resonance to be more like 3.6 mhz . 4.4. power planes or islands the imperfections of the power planes themselves have so far been ignored. these may also introduce unwanted resistance and inductance into the power distribution system. in the complex model in figure 3 these imperfections are referred to as r board and l board . power should definitely be distributed as a plane. this plane can be constructed as an island on a layer used for other signals, on a supply plane with other power islands, or as a dedicated layer of the printed circuit board (pcb). processor power should never be distributed by traces alone. see figure 20 for an example of a voltage island. due to the fact that the pentium pro processor voltage is unique to most system designs, a voltage island, or islands, will probably be the most cost effective means of distributing power to the processors. this island should be continuous from the source of power to the load. it should also completely surround all of the pins of the source and all of the pins of the load. figure 20 also shows the placement of an sma-type coaxial connection. this connection will later allow the direct connection of an oscilloscope for accurate power plane measurements. vccs vccp vccp d c-> dc conve rter w/ b u l k decoupling decoupling vccs vccp vccp d c-> dc conve rter w/ b u l k decoupling decoupling 2h 2 o n c s figure 20. a pentium ? pro processor voltage island e ap-523 23 4.4.1. location of high frequency decoupling high frequency decoupling should be placed as close to the power pins of the load as physically possible. use both sides of the board if necessary for placing components in order to achieve the optimum proximity to the power pins. this is vital as the inductance of the boards metal plane layers could cancel the usefulness of these low inductance components. another method to lower the inductance that should be considered is to shorten the path from the capacitor pads to the pins that it is decoupling. if possible, place the vias connecting to the planes within the pad of the capacitor. if this is not possible, keep the traces as short as is feasible. possibly one or both ends of the capacitor can be connected directly to the pin of the processor without the use of a via. even if simulation results look good, these practical suggestions can be used to create an even better decoupling situation where they can be applied in layout. figure 21 illustrates these concepts. 4.4.2. location of bulk decoupling the location of bulk capacitance is not as critical since more inductance is already expected for these components. however, knowing their location and the inductance values involved will be useful for simulation. in this example the bulk capacitance is on the voltage converter module electrically behind the inductance of the converter pins. this is intels recommended solution. 4.4.3. impedance and emission effects of power islands there are impedance consequences for signals that cross over or under the edges of the power island that exists on another layer. while neither of these may be necessary for most designs, there are two reasonable options to consider which can protect a system from these consequences. the pentium pro processor power islands can be isolated from signals by one of the solid power plane layers such as the ground layer. this forces a particular stack-up model. another option that helps, but does not completely eliminate radiation effects, is to decouple the edges of the cpu power islands to ground on regular intervals of about 1 using good high frequency decoupling capacitors (1206 packages). this requires more components but does not require any particular board stack-up. in either event, for controlling emissions, all planes and islands should be well decou pled. the amount of decoupling required for controlling emission will be determined by the exact board layout, and the chassis design. one should plan ahead by allowing additional pads for capacitors to be added in case they are discovered necessary during initial emi testing. 5.0. the gtl+ bus power requirements the gtl+ bus is an end terminated, open-drain bus. both ends are terminated to a voltage level called v tt (1.5v) which becomes a supply of current when output drivers are turned on. there are approximately 150 gtl+ lines in a pentium pro processor system design. the gtl+ bus power requirements present a different situation than creating power for the cpus. while the current required is less than that for a processor, the gtl+ bus does have a fairly tight tolerance specification. just as the processor can start and stop executing within a few clock cycles, the bus usage follows, which in turns causes load changes and transients on the gtl+ power supply (v tt ). since the gtl+ bus is terminated at both ends, v tt must be available to the termination resistors at both ends of the bus. this can be accomplished by having two sources of v tt or by distributing v tt . bad vias go od excellent p ads capacitors go od p in go od figure 21. 1206 capacitor pad and via layouts ap-523 e 24 table 4. estimating v tt current signal group quantity of signals maximum duty cycle average current data + ecc 72 100 3.24 address + parity 35 67 1.06 arbitration 7 100 0.32 request 7 67 0.21 error 5 20 0.05 response 6 33 0.09 other 9 100 0.41 total 141 5.38 the maximum current that a gtl+ buffer will sink is 45 ma. when considering the duty cycle of the signals, the maximum current that the 141 signals will draw is about 5.38 amps at 100% utilization of the bus. notice that the duty cycles are chosen rather conservatively in table 4. the actual current will be limited by the utilization of the bus and by the value of the termination resistors in the design. these benefits can be taken into account as well. 5.1. tolerance the tolerance specification is 150 mv. it is again important to note that this tolerance specification covers all voltage anomalies including power supply ripple, power supply tolerance, current transient response, and noise. not meeting the specification on the low or high end will change the rise and fall time specifications. failure to meet this specification on the low end will also result in reduced margins for the gtl+ buffers thus making it more difficult to meet timing specifications. 5.2. reference voltage the gtl+ bus requires a voltage reference called v ref as well. v ref is to be set at 2/3 v tt . the current draw on this signal is very low (at most 15 m a per device) and can be created by a simple voltage divider of two resistors. bear in mind that the leakage current can vary and may be significant when building the voltage divider. 6.0. meeting the gtl+ power requirements due to the different nature of powering the gtl+ bus versus powering a processor, meeting the v tt requirements may be addressed in a different way. 6.1. generating v tt since the gtl+ bus must be terminated on both ends of the bus, it may be convenient in many designs to generate v tt on each end of the line. each will only be required to supply one half of the current necessary to the gtl+ drivers. if both ends of the bus are fairly near each other, then one supply could suffice. when powering the bus from a single regulator, the techniques of design will closely resemble those of section 4 and a full analysis should be run. when powering each end of the bus separately, the current will be low enough that a linear regulator can reasonably be used to generate it. linear regulators are faster devices than switching regulators and will therefore require less output decoupling. also, due to the lower current, the esr and esl of components will not be as large an issue as before. a proper analysis as in described in section 4 could be considered. the techniques would remain the same, while the reaction time of the supply and the current levels will be different. it is not necessary for these two regulators to track each other as long as each maintains the specification on v tt . the bus will naturally perform an averaging function on these two inputs which must also be followed by v ref as discussed in section 6.3. 6.2. distributing v tt v tt is only needed at the termination resistors and for generation of v ref . if the distance to the termination resistors is small, distributing v tt with a wide trace should be sufficient. the trace to the v ref generation e ap-523 25 point should also be wide, even though the current is low, in order to keep its inductance minimal. if one source of the v tt voltage is used to power both ends of the bus, and the ends are not near each other, then a plane may be useful for v tt distribution. this will help offset the resistive and inductive losses that are an issue for v tt distribution just as they are issues for v cc p. separate smaller linear regulators at each end of the bus may alleviate the possible need for a power plane. note when using resistor networks with single corner pin v cc connections for gtl+ termination, beware of inductive packages. intel has found that these packages can cause significant voltage drops due to the inductance in the 24 pin soic packages being used for this purpose. 6.3. generating and distributing v ref v ref is a low current input to the differential receivers within each of the components on the gtl+ bus. as it is fairly low current (at most 15 m a per device), it can be generated by a simple voltage divider. because v ref is used only by the input buffers, it does not need to maintain a tight tolerance from component to component. it does however need to meet the 2% specification at all v ref inputs and should track the v tt averaging that occurs if using two regulators at opposite ends of the bus. the v ref specification is 2/3 v tt 2%. by using 1% resistors one can easily meet this specification. in figure 22, using r 1 = 2 r 2 , v ref is set at a nominal value of 2/3 v tt . equation 11. creating v ref of 2/3 v tt vv r rr v r rr v ref tt tt tt = + = + = 1 12 2 22 2 3 2 2 r 1 and r 2 should be small enough values that the current drawn by the v ref inputs (i ref ) is negligible versus the current caused by r 2 and r 1 . a complete analysis of this circuits currents into and out of the center node, as in equation 12, will provide the final v ref of the circuit. n is the number of i ref inputs supplied by the divider. r 2 v v tt r 1 v ref i s i ref ss figure 22. v ref equation 12. node analysis ir ir n i () () 21 =+ ref plugging in for the currents and rearranging, gives: equation 13. node analysis in terms of voltage vv r v r ni tt ref ref ref - -= 21 which leads to: equation 14. solving for v ref v vrni rr ref tt ref = - + 2 21 11 the worst case v ref should be analyzed with i ref at the maximum and minimum values determined for the number of loads being provided voltage. if the number of loads can change from model to model or because of upgrades, this should be taken into account as well. equation 14 should also be analyzed with r 1 and r 2 at the extremes of their tolerance specifications. ap-523 e 26 6.3.1. distributing v ref or v tt a resistor divider can be placed at each component by distributing v tt , or v ref can be generated at a voltage regulator and then distributed to each of the devices. to eliminate noise and losses on whichever level is distributed, use a wide isolated trace. the current should be fairly low in either case, but this extra width will help keep the induced noise level down. if more than one regulator is being used to generate v tt , then v ref must track them by averaging from both v tt sources. one method of accomplishing this is to generate a separate v ref at each regulator for up to four loads each, and then connect the two together with a wide trace. the closer this v ref signal tracks the path of the bus signals, the better it will match the averaging of the voltage on the gtl+ bus. however, this signal should be routed on a separate layer in order to keep cross-talk off of it. 7.0. recommendations designing and verifying ones own system using simulation is highly recommended. with the above estimates, a model of the power source, and the provided model of the pentium pro processor in section 11, analog modeling can be started. intel recommends the following as a starting point, or benchmark. 7.1. v cc s for v cc s, use a standard pc power supply with a 3.3v tap. be sure that there is sufficient current on the 3.3v tap of the supply to power all of the system chipset, the gtl+ regulator (if run off of 3.3v), other 3.3v logic in the system and any possible l2 caches that may someday exist in the system. see the chipset specification for chipset power requirements. see the flexible motherboard specifications in the pentium a pro processor developers manual, volume 1 for the requirements of the l2 cache. bulk decoupling requirements will be highly dependent on the reaction time of the power supply that is chosen. for high frequency decoupling, twenty (20) 0.1 m f capacitors in a 1206 package should be more than adequate. this should limit di/dt noise to 20 mv. while this sounds extravagant, it is wise to keep l2 noise isolated from other components that will be sharing the 3.3v supply, and vice versa. note that no decoupling is required when supporting only processors in which the l2 receives power from the v cc p pins. 7.2. v cc p -- figure 23. local regulation for v cc p, intel recommends starting with a socketed local dc-to-dc converter as shown in figure 23. this removes cable inductance from the distribution, reduces board inductance, and allows for a low cost upgrade strategy as well. regulator sockets can be provided for upgradable processor sockets rather than shipping with the full current capability already available. another benefit of using separate regulators per processor is the ability to mix and match processor types in the system. the output of this regulator should be adjustable to allow for changes in the voltage specification as new products become available. section 10 discusses recommended specifications for the dc-to-dc converter. these specifications have been provided to the dc-to-dc converter industry. intel recommends that the bulk decoupling be placed on this dc-to-dc converter module. since these capacitors tend to be large and not available in surface mount technology, it makes sense to isolate these to a smaller module that can be run in a different manufacturing environment than the typical system board designs. up to fourteen (14) 1000 m f electrolytic capacitors with an esr of less than 55 m w each should be placed on the converter module , depending on the switching rate of the converter. the high frequency decoupling should be composed of at least forty (40) 1.0 m f capaci tors in the 1206 package. ten or more are needed to meet the inductance requirements and 40 m f is required to slow the di/dt to 30a/ m s for the dc-to-dc converter specification. these should be placed close to the v cc p pins as shown in figure 20. an open centered socket will make this job easier and allow for the use of the space immediately under the processor. the plane can be constructed as an island as in figure 20 without any special isolation from the signal layers. e ap-523 27 7.2.1. the main power supply the main supply must be able to provide power to the dc-to-dc converter as well as to the rest of the system. one should ensure that the input voltage to the converter meets the converters requirements, and that the dc-to- dc converter does not create a transient problem of its own on the 5v or 12v outputs of the main supply. the guidelines that were given to the dc-to-dc converter industry are described in section 10.2, and should be checked against the supply that is planned for the system. for example, the current slew rate capability of the power supply voltage to the regulator may be 0.2 amp/ m s with 10,000 m f of load. 7.3. v tt intel recommends supplying v tt to each end of the gtl+ bus using a separate linear regulator for each end. since the losses in a linear regulator are directly proportional to v in -v out , the 3.3v power supply makes a good choice for the input voltage to the regula tor. the cpu voltage may seem like a better choice if it is lower than 3.3v, but it will be varying from one pentium pro processor variant to the next. this may cause a design change for each generation of pentium pro processor. also, linear regulators require a minimum voltage drop in order to operate which may become an issue as the pentium pro processor voltage decreases. by using separate linear regulators, the voltage distribution is contained to a very local region. in a bus layout where both ends of the bus are physically near each other, one regulator can be used to supply both sets of termination resistors. in this situation, a 50 mil trace (the wider the better) should be sufficient for distributing the power to the termination resistors. linear regulators are fairly common and produced by many vendors. see your local field applications engineer for assistance locating a vendor. bulk capacitance for the regulator will be determined from the reaction time specifications of the regulator chosen. the capacitance must be enough to hold-over the regulator during a switch from 0 to 5.4 amps, as estimated in table 4, until the regulator reacts. in addition, ten 1.0 m f capacitors are recommended for high frequency decoupling on each end of the pentium pro processor bus. these should be distributed as near to the termination resistors as possible. 7.3.1. termination resistors discrete resistors may be employed, however the assembly time associated with placing about 280 resistors should be taken into account. a lower part count implementation uses resistor networks. note when using resistor networks with single corner pin vcc connections for gtl+ termination, beware of inductive packages. intel has found that these packages can cause significant voltage drops due to the inductance in the 24 pin soic packages being used for this purpose. a better option is to use resistor networks in which both ends of each resistor are available as pins. 7.4. v ref intel recommends one voltage divider at each component, or at a minimum, one voltage divider at each regulator. one per component means that v ref wont need to be distributed. the rest of this discussion addresses how to design for one voltage divider at each regulator, since the same resistor values can be used when there is one voltage divider per component. note that all v ref inputs of one component should be tied together, and can be counted as one load. each load is specified at a maximum of 15 m amps of leakage current which makes four loads (for one voltage divider supplying 4 loads of an 8 load system) a maximum of 60 m amps per voltage divider. note that these leakage currents can be positive or negative. using 1% resistors for the voltage divider in figure 24, make r 1 a 150 w resistor, and use 75 w for r 2 . this will create a static usage of 7 ma (1.5v/225 w ) per voltage divider. after looking at all combinations of r 1 and r 2 (above and below tolerance) and i ref ( 60 m a), the worst case solution for equation 14 can be found with i ref at 60 m amps, r 1 at the low end of its tolerance specification (148.5 w ), and r 2 at the high end of its tolerance specification (75.75 w ). this yields: ap-523 e 28 r 2 v v tt r 1 v ref i s i ref ss figure 24. generating v ref equation 15. resistor tolerance analysis vv ref = - + ? 1 5 75 75 000060 1 75 75 1 148 5 099 ... .. . since the target of 2/3 of v tt is 1.00v, this setting is within 0.97% of the 2/3 point and satisfies the 2% specification. the other corners can be easily verified by the reader through the use of a spreadsheet program. v tt can also be varied over its tolerance range, but this effect is minimal. these values chosen for r 1 and r 2 have additional benefits. the parallel combination terminates the v ref line to 50 ohms, and both are standard values of resistors which should benefit their cost. v ref should be decoupled with a 0.001 m f capacitor to v ss located at each v ref input and at the voltage divider. at the voltage dividers, v ref can also be decoupled with a 0.001 m f capacitor to v tt to further enhance the ability for v ref to track v tt . the actual benefit of this controversial. when routing v ref to the loads, use a 30-50 mil trace (the wider the better) and keep all other signals at least 20 mils away from the v ref trace. this will provide a low impedance line without the cost of an additional plane or island. finally, if generating v ref at the voltage regulators, both v ref levels should be tied together in order to provide an automatic averaging across all devices to match the natural averaging that occurs between the two regulators over the gtl+ bus signals. if possible, use a separate layer from the gtl+ signal layers and follow the path of the bus signals. this will provide the best averaging effect. 7.5. component models component models should be acquired from the manufacturers. intel can not guarantee the specifications of another manufacturers components. this section contains some of the models that intel has developed for its simulations. the pentium pro processor model can be found in section 11. table 5. various component models used at intel (not vendor specifications) component of simulation esr ( w w ) esl (nh) esl+ trace + via (nh) 0.1 m f ceramic 0603 package 0.100 1.60 3.0 1.0 m f ceramic 1206 package 0.120 0.47 1.9 100 m f mlc (2.05x0.71) 0.005 0.30 1.7 47 m f, 16v tantalum d case 0.100 0.602 2.0 330 m f, 16v aluminum electrolytic 0.143 2.37 3.8 1000 m f, 10v aluminum electrolytic (20mm) 0.053 n/a n/a 1000 m f, 25v aluminum electrolytic (25mm) 0.031 n/a n/a l board . one used for v ss , one for v cc p. this estimate accommodates traces to vias, planes and the socket connections to the plane. 0.000 0.40 n/a e ap-523 29 8.0. measuring transients in order to measure transients on a voltage island, a clean connection will be required. a good way to achieve this is by the placement of a coaxial connection directly into the power island during layout. an sma type connector can be used and should be placed near the centrum of the array of pins receiving that voltage as in figure 20.since a cable will mate to this connector while the system is functioning, this connector must be placed on the opposite side of the board as the processor. cable the signal directly into the oscilloscope and take the reading with the oscilloscope bandwidth limited to 20mhz. this will filter out the components of the vcc noise that the package characteristics also filter out. there is no need to decouple frequencies above this range since these frequency components will not enter the pentium pro processor package. 9.0. existing technology for a pentium a a pro processor system design 9.1. solutions for v cc p intel has assisted in the development of many industry dc-to-dc converter modules for the pentium pro processor. any of these components used in a specific design should be understood by the designer and can not be guaranteed by intel for use in that design. in general, the vendor of any component will assist in the usage of their component. see your local field office for a list of possible vendor solutions. another solution that is a simple extension to the discussion in this paper is to integrate the components of the dc-to-dc converter, including the bulk capacitance, onto the system pcb. intel has helped power silicon vendors as well in designing pentium pro processor specific solutions. again, see your local field office for a list of possible vendor solutions. 9.2. linear regulators for v tt linear regulators are widely available. switching regulators can also be used to generate v tt . 9.3. termination resistors intel recommends the use of resistor networks to reduce the part count of the processor board assembly. the best options are resistor networks with separate pin access to each side of every resistor in the package. this will minimize any inductance or crosstalk within the package. when using resistor networks with single corner pin v cc connections for gtl+ termination, beware of inductive packages. intel has found that these packages can cause significant voltage drops due to the inductance in the 24 pin soic packages being used for this purpose. 10.0. dc-to-dc converter specifications the following specifications define dc-to-dc converters to meet the requirements of the pentium pro processor and future intel microprocessors. each specification is placed into one of three categories: required : an essential part of the design; cannot meet minimum pentium pro processor specifications without it. expected : part of intels standard pentium pro processor power definitions; necessary for consistency with the designs of many systems and power devices. required by most pentium pro processor flexible motherboard designs. guideline : normally met by of this type of dc-to-dc converter and, therefore, included as a design target. likely to be specified by system manufacturers. 10.1. electrical specifications specification summary required the dc-to-dc converter must meet the specifications for any processor it is intended to power in a system. for example, table 6 shows the specifications for a dc-dc converter to support a 150 mhz pentium pro processor with a 256-kbyte l2 cache. converters supporting the requirements of a pentium pro processor flexible motherboard must meet the broader requirements of table 8. ap-523 e 30 table 6. 150 mhz, 256-kbyte l2 cache pentium pro ? processor voltage and current specifications parameter value voltage 3.1v 5% current 0.3 - 9.9a slew rate 30a/ m s at converter pins 10.1.1. input voltages available inputs are at 12v 5% and at 5v 5%. either one or both of these inputs may be used by the converter. the vendor must provide maximum current loading requirements on all inputs. these voltages are supplied by a conventional pc power supply through a cable to the motherboard. load transient effects on input voltages guideline the converter must be able to provide for an output current step at the load from i min to i peak (per table 7) in 360 ns. during this step response the input current di/dt must not exceed 0.1 amps/ m s. for applications with multiple converters, it is recommended that the step response di/dt of an individual converter not exceed 0.04 amps/ m s. 10.1.2. i/o controls these are signals that control the dc-to-dc converter or provide feedback from the dc-to-dc converter (shown with corresponding pins in table 10). input and output levels must be consistent with ttl dc specifications. power-good (pwrgd) guideline an open collector signal must be provided. when the output voltage is not within specifications (nominal or selected voltage 10%) this signal must be at the low state. this signal must transition to the proper state within 5 milliseconds of the output coming into or going out of its specified range. output enable (outen) guideline the module must accept an open collector signal for controlling the output voltage: the low state must disable the output voltage. when disabled, the pwrgd output must be in the low state. upgrade present (up#) expected the module must accept an open collector signal, used to indicate the presence of an upgrade processor. typical state is high (standard processor in system). when in the low or ground state (overdrive processor in system) the output voltage must be disabled unless the converter can supply to an overdrive processors specifications (see table 8). when disabled, the pwrgd output must be in the low state. voltage identification (vid[0:3]) expected the module must accept four signals, used to indicate the voltage required by the processor, as defined by table 9. 10.1.3. output requirements dc output current required the dc output current requirements corresponding to the processor in table 6 are shown in table 7. table 7. dc output current parameter value i min 0.3 amps i max 9.9 amps i peak (several m s of overshoot) 11 amps voltage range by application expected a pentium pro processor-based system may require one of the adjustment ranges shown in table 8. the i cc column represents the current requirement intel expects for processors at each voltage. processor voltage identification expected the adjustment mechanism must be by four binary weighted inputs using the coding described in table 9. e ap-523 31 four pentium pro processor pins will have an openC ground pattern corresponding to the voltage required by the individual processor unit. voltages outside of the 2.4- volt to 3.5-volt range may be considered optional for use by the module supplier and system manufacturer. table 8. voltage ranges application support v min v max i cc pentium ? pro processor 2.9 volts 3.5 volts (up to) 13 amps pentium pro processor + overdrive ? processor upgrade 2.4 volts 3.5 volts 13 amps table 9. voltage identification code pentium? pro processor pins v cc p vid3 vid2 vid1 vid0 (vdc) 1 1 1 1 no cpu 1 1 1 0 2.1 1 1 0 1 2.2 1 1 0 0 2.3 1 0 1 1 2.4 1 0 1 0 2.5 1 0 0 1 2.6 1 0 0 0 2.7 0 1 1 1 2.8 0 1 1 0 2.9 0 1 0 1 3.0 0 1 0 0 3.1 0 0 1 1 3.2 0 0 1 0 3.3 0 0 0 1 3.4 0 0 0 0 3.5 notes: 0 = processor pin connected to v ss 1 = processor pin open (system design may include pull-up resistor to voltage consistent with ttl input levels) ap-523 e 32 dc voltage regulation required voltage regulation limits must include: output load ranges specified in table 8 . output ripple/noise. dc output initial voltage set point adjust temperature and warm up drift specified in table 11. output load transient (slew rate) as defined in table 6. the toggle rate for the output load ranges specified in this section must range from 100 hz to 100 khz. under the above conditions and for all toggle rates, voltage levels must be 5% of nominal setting, as measured over a 20 mhz frequency band. output ripple and noise guideline ripple and noise are defined as periodic or random signals over the frequency band of 20 mhz at the output pins. output ripple and noise requirements of 1.0% must be met throughout the full load range and under all specified input voltage conditions. variation with load guideline to assist in providing margin during high slew rate current load transitions, the vendor may target module performance so as to provide for a nominal +2% offset when under minimum load conditions, and a nominal -2% offset when under maximum load conditions. overshoot at turn-on/turn-off guideline overshoot upon the application or removal of the input voltage under the conditions specified in this section must be less than 10% above the initial set output voltage. no voltage of opposite polarity must be present on any output during turn-on or turn-off. turn-on response time guideline the output voltage must reach 99% of nominal level within 10 ms of the input reaching 90% of nominal level. efficiency guideline the efficiency of the dc-to-dc converter must be greater than 80% at high current draw and greater than 40% at low current draw. 10.1.4. protection these are features built in to the dc-to-dc converter to prevent damage to itself or the circuits it powers. over-voltage protection (ovp) guideline protection level: the converter must provide over- voltage protection by shutting itself off when the output voltage rises beyond v trip . v trip must be set between 10% and 20% above the selected output voltage level. short circuit protection guideline a load short circuit is defined as a load impedance of less than approximately 200 m w . the dc-to-dc converter must operate in a constant current mode for a shorted output. the dc-to-dc converter must be capable of withstanding a continuous short-circuit to the output without damage or over-stress to the unit. reset after shutdown guideline if the dc-to-dc converter goes into a shutdown state due to a fault condition on its outputs, the dc-to-dc converter must return to normal operation after the fault has been removed, or after the fault has been removed and power has been cycled off and on. voltage sequencing required no combination of input voltages may falsely trigger an ovp event. e ap-523 33 10.2. mechanical requirements 10.2.1. physical description dimensions expected outline dimensions must be equal to or less than 3.1 x 1.5 x 1.0. maximum component height must be 0.80" on the connector side and 0.14" on the back side of the module. figure 26 shows the outline of a module board. a20 b20 a1 b1 figure 25. pin orientation (top view) interconnect expected interconnect must consist of a 40 pin interface with the socket (type ampmod2, part number 532956-7, or equivalent) mounted to the module. figure 25 shows the pin orientation of the dc-to-dc converter, and figure 27 shows the connector features. the baseboard interface pins must conform to intels voltage regulator module 8 header, revision 3.0 (vrm 8, see figure 28). the current capacity must be at least 2 amps/pin. the pin electrical interface is given in table 10. table 10. pin definitions pin # row a row b 15v in 5v in 25v in 5v in 35v in 5v in 4 12v in 12v in 5 12v in 1 reserved 6 reserved outen 7 vid0 vid1 8 vid2 vid3 9 up# pwrgd 10 v cc pv ss 11 v ss v cc p 12 v cc pv ss 13 v ss v cc p 14 v cc pv ss 15 v ss v cc p 16 v cc pv ss 17 v ss v cc p 18 v cc pv ss 19 v ss v cc p 20 v cc pv ss note: connection to a5 is optional for a 12v input of less than 4 amps. ap-523 e 34 figure 26. module printed wiring board (dimensions in mm) figure 27. module connector features (dimensions in mm) e ap-523 35 figure 28. mating header (dimensions in mm) weight expected package weight, including any integral heat sink, must be less than three ounces. 10.2.2. mechanical interface mating header reference the vrm 8 header (see figure 28) is a 40-position, two- row, shrouded header with straight posts on 0.1 inch centers (amp part number 146315-1 or equivalent). the complete, current vrm 8 specification is available from intels end user component division (overdrive processors). baseboard attachment expected the voltage regulator module is to be retained to and removed from the header by features on the header that mate with the voltage regulator module. the removal and installation process must not require the use of tools. the removal features must be accessible from the back side (opposite the receptacle) of the module. alternative baseboard attachment reference an alternative mounting configuration is shown figure 29. in this configuration the baseboard interface must be a non-shrouded connector (type ampmod2, part number 2-103783-0 or equivalent). this mounting configuration is recommended for applications where, under normal usage, the module would not be removed after installation. ap-523 e 36 10.3. tests and standards environmental guideline design, including materials, must be consistent with the manufacture of units that meet the environmental standards in table 11. table 11. environmental guidelines operating non-operating temperature ambient +10c to +60c at full load with a maximum rate of change of 5c per 10 minutes minimum but no more than 10c per hour ambient C 40c to 70c with a maximum rate of change of 20c/hour. 1 humidity to 85% relative humidity. to 95% relative humidity. altitude 0 to 10,000 feet 0 to 50,000 feet. electrostatic discharge 15 kv initialization level. the direct esd event must cause no out-of-regulation conditions. 2 25 kv initialization level. notes: 1 thermal shock of C40c to +70c, 10 cycles; transfer time must not exceed 5 minutes, duration of exposure to temperature extremes must be 20 minutes. 2 includes overshoot, undershoot, and nuisance trips of the over-voltage protection, over-current protection or remote shutdown circuitry. e ap-523 37 figure 29. alternative mounting configuration - baseboard pattern (top view, dimensions in inches) ap-523 e 38 shock and vibration guideline the dc-to-dc converter must not be damaged and the interconnect integrity not compromised during: a shock of 50g with an 11 millisecond half sine wave, non-operating, the shock to be applied in each of the orthogonal axes. vibration of 0.01g 2 per hz at 5 hz, sloping to 0.02g 2 per hz at 20 hz and maintaining 0.02g 2 per hz from 20 hz to 500 hz, non-operating, applied in each of the orthogonal axes. electromagnetic guideline design, including materials, must be consistent with the manufacture of units that comply with the limits of fcc class b and vde 243 level b for radiated emissions, given the existence of an external package around the converter with 20 db of shielding. reliability guideline the converter must be designed to function to electrical specifications, within the environmental specifications, with 60c air at a velocity of 100 lfm directed along the connector axis. 10.3.1. component de-rating guideline the following component de-rating guidelines must be followed: semiconductor junction temperatures must be < 115c with ambient at 50c. capacitor case temperature must not exceed 80% of rated temperature. resistor wattage de-rating must be > 50%. component voltage and current de-rating must be > 20%, the effects of ripple current heating must be accounted for in this de-rating. 10.3.2. mean time between failures (mtbf) guideline design, including materials, must be consistent with the manufacture of units with an mtbf of 500,000 hours of continuous operation at 55c, maximum-outputs load, and worst-case line, while meeting specified requirements. mtbf must be calculated in accordance with mil-std-217f. safety guideline design, including materials, must be consistent with the manufacture of units that meet the standards of ul flammability specifications per 94v-0. 11.0 pentium ? pro processor power distribution network modeling the following power model is provided in hspice format to allow simulation of the power distribution sub- system. this is the same model used by intel for simulation of early power supply solutions. it is a norton equivalent circuit created to estimate a worst case di/dt of about 1.0a/ns with a peak current of 10 amps and a minimum current of 0a. this model is for a 150mhz clock and includes the switching transients that can occur during full power operation, as well as the initial current ramp from low to high current states. a similar effect occurs when entering stop clock from full power. this can also be modeled by changing this model symetrically. this information should be used solely as a baseline for system development and should be followed by actual measurements of the power islands as explained in section 8. 11.1. using the power distribution model this model assumes a peak current of 10 amps and a minimum current of 0 amps. this is only a slightly wider swing than the specification for the 150mhz pentium pro processor. to design for a flexible motherboard, one should scale this model upwards. note that a change in frequency will affect this model somewhat, but not drastically. this model includes a socket that meets the guideline of 4.5nh mated inductance per pin. do not add a socket into your model as this is already comprehended in the pentium pro processor power model. the model presented here has been shown to correlate with the intels internal models within the range of normal operation. however, as the voltage at the pentium pro processor pins departs from the 5% voltage e ap-523 39 specification, the accuracy will suffer. specifically, the pentium pro processor die will consume more current at high voltage and less current at low voltage while the spice model does not exhibit this behavior. therefore, bear in mind that while this model can be used to accurately model a system that meets or exceeds the 5% voltage requirement, it cannot be used to accurately describe how far out of specification a poorly designed system lies. 11.2. power distribution model this is the hspice format power distribution model for a socketed pentium pro processor. the schematic is shown in figure 30. note that the last line of the model includes r 73.9ns. this commands the simulator to continuously repeat the last portion of the waveform from time 73.9ns until the end of the simulation. ri 100 101 0.01 li 101 102 121ph ci 102 103 160nf ipulse 100 103 pwl(0 0 4.1ns 0 18.8ns 14.78 + 20ns 13.78 22ns 13.48 27.3ns 10.31 + 31.8ns 7.874 + 35ns 10.668 39.5ns 8.17 + 42.9ns 8.91 45.5ns 8.574 47.1ns 7.514 + 50.1ns 8.633 56. 4ns 11.08 + 58.5ns 10.77 + 61.8ns 13.71 67.5ns 9.17 + 72.3ns 7.26 + 73.9ns 5.91 77.8ns 7.20 83.4ns 11.11 + 85.4ns 11.26 88.6ns 14.54 95.9 ns 9.11 + 100.8ns 5.576 r 73.9ns) i sc 121ph li 160nf ci .01 ohms ri 100 103 101 102 pin pin figure 30. socketed pentium a a pro processor power distribution model schematic figure 31 shows the short-circuit current used in the hspice model plotted vs. time. 0 2 4 6 8 10 12 14 16 18 time (ns) c u r r e n t ( a m p s ) figure 31. power distribution model short-circuit current |
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